MAX1434ECQ+D【PDF 2/22 页】IC ADC 10BIT 50MSPS 100-TQFP

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MAX1434

Octal, 10-Bit, 50Msps, 1.8V ADC

with Serial LVDS Outputs

______________________________________________________________________________________

PIN

NAME

FUNCTION

1, 4, 7, 10, 16, 19, 22,

25, 26, 27, 30, 36, 89,

92, 96, 99, 100

GND

Ground. Connect all GND pins to the same potential.

IN1P

Channel 1 Positive Analog Input

IN1N

Channel 1 Negative Analog Input

IN2P

Channel 2 Positive Analog Input

IN2N

Channel 2 Negative Analog Input

IN3P

Channel 3 Positive Analog Input

IN3N

Channel 3 Negative Analog Input

11, 12, 13, 15, 37–42,

86, 87, 88

AVDD

Analog Power Input. Connect AVDD to a +1.7V to +1.9V power supply. Bypass AVDD to GND

with a 0.1F capacitor as close as possible to the device. Bypass the AVDD power plane to

the GND plane with a bulk

≥ 2.2F capacitor. Connect all AVDD pins to the same potential.

14, 31, 50, 51, 70,

75, 76

N.C.

No Connection. Not internally connected.

IN4P

Channel 4 Positive Analog Input

IN4N

Channel 4 Negative Analog Input

IN5P

Channel 5 Positive Analog Input

IN5N

Channel 5 Negative Analog Input

IN6P

Channel 6 Positive Analog Input

IN6N

Channel 6 Negative Analog Input

IN7P

Channel 7 Positive Analog Input

IN7N

Channel 7 Negative Analog Input

Double-Termination Select. Drive DT high to select the internal 100

termination between the

differential output pairs. Drive DT low to select no output termination.

SLVS/LVDS

Differential Output-Signal Format-Select Input. Drive SLVS/LVDS high to select SLVS outputs.

Drive SLVS/LVDS low to select LVDS outputs.

CVDD

Clock Power Input. Connect CVDD to a +1.7V to +3.6V power supply. Bypass CVDD to GND

with a 0.1F capacitor in parallel with a

≥ 2.2F capacitor. Install the bypass capacitors as

close as possible to the device.

CLK

Single-Ended CMOS Clock Input

43, 46, 49, 54, 57, 60,

63, 64, 67, 71, 74, 77

OVDD

Output-Driver Power Input. Connect OVDD to a +1.7V to +1.9V power supply. Bypass OVDD to

GND with a 0.1F capacitor as close as possible to the device. Bypass the OVDD power plane

to the GND plane with a bulk

≥ 2.2F capacitor. Connect all OVDD pins to the same potential.

OUT7N

Channel 7 Negative LVDS/SLVS Output

OUT7P

Channel 7 Positive LVDS/SLVS Output

OUT6N

Channel 6 Negative LVDS/SLVS Output

OUT6P

Channel 6 Positive LVDS/SLVS Output

OUT5N

Channel 5 Negative LVDS/SLVS Output

OUT5P

Channel 5 Positive LVDS/SLVS Output

OUT4N

Channel 4 Negative LVDS/SLVS Output

OUT4P

Channel 4 Positive LVDS/SLVS Output

Pin Description

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